File name 28C513.pdfCAT28C512/513
512K-Bit CMOS PARALLEL EEPROM FEATURES
s Fast Read Access Times: 120/150 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation:
Active: 50 mA Max. Standby: 200 µA Max.
s Simple Write Operation:
1 to 128 Bytes in 5ms Page Load Timer
s End of Write Detection:
On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
Toggle Bit DATA Polling DATA
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive
5ms Max
s CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS parallel EEPROM organized as 64K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C512/513 features hardware and software write protection. The CAT28C512/513 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin TSOP packages.
BLOCK DIAGRAM
ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 65,536 x 8 E2PROM ARRAY 128 BYTE PAGE REGISTER
A7A15
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
I/O0I/O7
A0A6
ADDR. BUFFER & LATCHES
5096 FHD F02
© 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 1007, Rev. C
CAT28C512/513
PIN CONFIGURATION
DIP Package (P)
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PLCC Package (N)
NC VCC WE A12 A15 NC NC
PLCC Package (N)
A14 A15 VCC WE A7 A12 A13
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 CAT28C512 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20
4 3 2 1 32 31 30
A14 A13 A8 A9 A11 OE A10 CE I/O7
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 CAT28C513 TOP VIEW
29 28 27 26 25 24 23
A8 A9 A11 NC OE A10 CE I/O7 I/O6
12 22 13 21 14 15 16 17 18 19 20
I/O1 I/O2 VSS NC I/O3 I/O4 I/O5
I/O1 I/O2 VSS I/O3 I/O4 I/O5
I/O6
5096 FHD F01
TSOP Package (8mmx20mm) (T)
A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CAT28C512
TOP VIEW
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A3
PIN FUNCTIONS Pin Name A0A15 I/O0I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Wr |